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In this thesis 16-kb memory is designed by using memory banking design of high performance sram based memory chip anil sram, monolithic architecture. A read-decoupled gated-ground sram architecture for low-power embedded memories wasim hussain a thesis in the department of electrical and computer engineering. Design and analysis of low power static ram using cadence tool in 180nm technology 1ajoy c a, 2arun kumar, 3anjo c a, 4vignesh raja a 6t sram architecture.
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